1. Field of the Invention
The present invention relates to a semiconductor device isolation structure and a semiconductor device fabrication method using the same.
2. Description of the Prior Art
A junction isolation structure is not appropriate under high voltage and high radioactive environments. This is because a high voltage supply of about 30V may lead to a junction breakdown, and a photo-electric current generated in a pn junction by gamma rays may be transient under high radioactive environments. A SOI (Silicon On Insulator) technology is a device isolation method for entirely surrounding a semiconductor device with an insulator rather than adopting a pn junction isolation structure, enabling operation notwithstanding the existence of high voltage and high radioactive environments.
In the SOI technology, fabrication steps are more simplified than fabrication steps required for a circuit formed from bulk silicon. Furthermore, using the SOI technology, a latch-up is prevented in a CMOS (Complementary Metal Oxide Semiconductor) circuit. Still further, using the SOI technology, capacitive coupling between circuits is decreased in an identical semiconductor substrate, leading to a decrease in the semiconductor chip size.
U.S. Pat. No. 5,438,015 discloses an SOI related convention art using a buried air gap, which SOI technology will be described with reference to FIGS. 1A through 1D.
First, as shown in FIG. 1A, a field oxide film 31 is formed via a general LOCOS (LOCos Oxidation of Silicon) method. In the conventional art, the field oxide film 31 is preferably from about 3000 A to 10000 A in thickness.
As further shown in FIG. 1B, using the field oxide film 31 on the semiconductor substrate 30 as a mask, nitride ions are implanted into the substrate 30 at a density ranging from 1.times.10.sup.18 to 2.times.10.sup.18 atoms/cm.sup.2 and an energy of 100.about.200 KeV. The resulting structure is then annealed for about 1 to 5 hours at a temperature ranging from 1100.degree. C. to 1300.degree. C. to form buried silicon nitride layers 32, whereby a plurality of active regions 33 are isolated by the buried silicon nitride layers 32 and the field oxide film 31.
Referring to FIG. 1C, a plurality of holes 34 are formed adjacent to edge portions, the holes being formed sufficiently deep to reach the buried silicon nitride layers 32. The semiconductor substrate 30 is then dipped into a hot phosphoric acid solvent, which has the characteristics of an etchant. When dipped, the solvent flows to the buried silicon nitride layers 32 through the holes 34 and etches those buried silicon nitride layers 32 to form buried gaps 35.
With reference to FIG. 1D, in order to carry out an annealing process and to compensate for possible defects in the semiconductor substrate 30, the holes 34 are filled with a silicon oxide material or a silicon nitride material via CVD (Chemical Vapor Deposition) method or a PVD (Physical Vapor Deposition) method. Reference numeral 36 denotes the silicon oxide material or the silicon nitride material which is stuffed in the holes 34. Then, the semiconductor substrate 30 is annealed at a temperature ranging from 900.about.1000.degree. C. In addition, to improve a device isolation effect, a silicon oxide film may be formed in the buried gaps prior to filling the holes 34 therewith.
When the device isolation process is completed, devices such as a gate electrode, a source and a drain are formed on the active region 33.
However because such an SOI technique employs a LOCOS method, it has been difficult to overcome disadvantages that belong to the conventional device isolation technique employing a LOCOS method. That is, a bird's beak formation confines the decrease of the active regions, thereby deteriorating integration in the semiconductor device.
Further, because of the bird's beak phenomenon, the implanted depth becomes different depending on whether it is an edge portion or a central portion on the active region when nitride ions are implanted into the substrate for forming the buried insulator. The differentiated depths may cause a threshold voltage variation on the active region. Also, a stress-oriented defect may be encountered when the field oxide film is formed adjacent to the bird's beak in the substrate.